The recent miniaturization of DRAM (Dynamic Random Access Memory) cells has been accompanied by the necessity of shortening the gate length of memory cell transistors. However, short channel effects in a transistor become more severe as the gate length is shortened, and drawbacks occur whereby sub-threshold current increases. When the substrate impurity concentration is increased in order to minimize this effect, deterioration of the refresh characteristics in the DRAM is a severe drawback because of increased junction leakage.
A so-called trench-gate transistor (also referred to as a recess-channel transistor) in which a gate electrode is embedded in a groove formed on a silicon substrate has been emphasized as a means of overcoming these drawbacks (see Japanese Laid-open Patent Application Nos. H9-232535, 2001-210801, 2005-142203, H7-066297, and 2004-014696). Using a trench-gate transistor, the effective channel length (gate length) can be physically and adequately maintained, and it is possible to create precision DRAM having a minimum feature size of 90 nm or less.
It has become necessary to employ transistors having a dual-gate structure in the peripheral circuit region of DRAM in order to provide increased performance and reduced drive voltage in a device. In a dual-gate structure, a gate electrode that includes N-type polycrystalline silicon, into which an N-type impurity (phosphorus or the like) is introduced, is used as the gate electrode of an N-channel transistor, and a gate electrode that includes P-type polycrystalline silicon, into which a P-type impurity (boron or the like) is introduced, is used in a P-channel transistor.
However, such drawbacks as the following occur when transistors having the two structures described above are used jointly in a single semiconductor device. Specifically, the following drawbacks occur when a trench-gate transistor is formed in the memory cell region, and a dual-gate transistor is formed in the peripheral circuit region.
The general method for forming the gate electrodes of a trench-gate transistor and a dual-gate transistor will first be described.
A gate electrode in a trench-gate transistor is formed by a process in which a groove (gate trench) is formed in a semiconductor substrate, and a gate insulating film is formed on the inner wall of the gate trench, after which a doped silicon film as a gate electrode material is embedded in the gate trench.
On the other hand, the gate electrode of a dual-gate transistor is formed by a method in which a non-doped silicon film is formed on a gate insulating film that is formed on a semiconductor substrate, after which a region in which an N-channel transistor is formed is covered by a resist mask, and a P-type impurity is introduced into a region for forming a P-channel transistor. The region in which the P-channel transistor is formed is then covered by a resist mask, and an N-type impurity is introduced into the region in which the N-channel transistor is formed, after which the P-type silicon film and N-type silicon film are patterned in the shape of a gate electrode.
Accordingly, two methods of the type described below may be used to form a trench-gate transistor in a memory cell region and to form a dual-gate transistor in a peripheral circuit region. These two methods will be described using FIGS. 21 through 27 below. In FIGS. 21 through 27, “region M” indicates the memory cell region, and “region P” and “region N” are provided to the peripheral circuit region, wherein “region P” is a region in which a P-channel transistor provided with a gate electrode that includes P-type polycrystalline silicon is formed, and “region N” is a region in which an N-channel transistor provided with a gate electrode that includes N-type polycrystalline silicon is formed.
The first method (hereinafter referred to as the first conventional method) will be described using FIGS. 21 through 24.
As shown in FIG. 21, a gate trench 202 is first formed in region M of a semiconductor substrate 200 whose regions are separated by an STI (Shallow Trench Isolation) 201, and a gate insulating film 203 is then formed on the entire surface that includes the inner wall of the gate trench 202. A non-doped silicon film 204 is then formed on the entire surface that includes the inside of the gate trench 202, as shown in FIG. 22. As shown in FIG. 23, regions M and N are then covered by a resist mask 205, a P-type impurity (boron, for example) is ion-implanted into region P, and the resist mask 205 is removed. Then, region P is covered by a resist mask 206, and an N-type impurity (phosphorus, for example) is ion-implanted into regions M and N, as shown in FIG. 24. The silicon films 204 of each region are then patterned into the shape of a gate electrode.
However, in this first conventional method, when ion implantation is performed according to the thickness (depth) of the silicon film 204 on region N in the process shown in FIG. 24, the silicon film 204 inside the gate trench 202 cannot be adequately doped with the N-type impurity, the trench-gate electrode becomes depleted, and it becomes impossible to demonstrate adequate performance in a memory cell transistor. Conversely, when the N-type impurity is ion-implanted according to the depth of the gate trench 202, the impurity cannot be introduced at a suitable concentration into the silicon film 204 on region N, and the impurity is introduced into the silicon substrate 200 in which the channel region and source/drain region are formed. There is therefore an adverse effect on the operation of both the memory cell transistor formed in region M and the transistor formed in region N.
Another method (hereinafter referred to as the second conventional method) such as the one described below may be used to prevent the type of drawbacks encountered in the first conventional method.
After a gate trench 202 and a gate insulating film 203 are first formed in the same manner as shown in FIG. 21, an impurity-doped silicon film (doped silicon film) 304a is formed on the entire surface that includes the inside of the gate trench 202, as shown in FIG. 25. As shown in FIG. 26, the entire surface is then etched back so as to leave the doped silicon film 304a only in the gate trench 202. A non-doped silicon film 304b is then formed on the entire surface, as shown in FIG. 27, and impurities are ion-implanted into the non-doped silicon film 304b in the same manner as in FIGS. 23 and 24.
According to this method, the doped silicon film 304a is embedded in the gate trench 202, and the problem of depletion of the trench-gate electrode is therefore overcome. Ion implantation can also be performed appropriately according to the thickness of the non-doped silicon film 304b when impurities are ion implanted in the same manner as in FIGS. 23 and 24, and it is possible to prevent impurities from being introduced into the silicon substrate 200.
However, the drawbacks that occur in the second conventional method are different from those of the first conventional method. Specifically, etching back the entire surface as shown in FIG. 26 causes the gate insulating film 203 to be damaged. A heat treatment and an oxidation process must be performed in order to repair the damage to the gate insulating film 203. A high-resistance layer is therefore formed on the surface of the doped silicon film 304a following the etch-back shown in FIG. 26. Because the high-resistance layer intervenes between the doped silicon film 304a and the non-doped silicon film 304b, the gate resistance increases.